1. Field of the Invention
Generally, the present disclosure relates to highly sophisticated integrated circuits including transistor elements having a double gate or triple gate architecture (FinFET).
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface positioned between highly doped regions, referred to as drain and source regions, and a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and thus allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. The threshold voltage is the voltage applied across the gate electrode and the transistor body at which a conductive channel begins to form in the channel region. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current, while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. The relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may not be compatible with requirements for performance driven circuits.
In view of further device scaling, possibly based on well-established materials, new transistor configurations have been proposed in which a “three dimensional” architecture is provided in an attempt to obtain a desired channel width, while at the same time superior controllability of the current flow through the channel region is preserved. To this end, so-called FinFETs have been proposed in which a thin sliver or fin of silicon is formed in a silicon layer of substrate, wherein on both sidewalls and, if desired, on a top surface, a gate dielectric material and a gate electrode material are provided, thereby realizing a multiple gate transistor whose channel region may be fully depleted. For convenience, the terms multiple gate transistor and FinFET will be used herein as interchangeable terms. Typically, in sophisticated applications, the width of the silicon fins is on the order of magnitude of 10-25 nm and the height thereof is on the order of magnitude of 30-40 nm. In some conventional approaches for forming FinFETs, the fins are formed as elongated device features followed by the deposition of the gate electrode materials, possibly in combination with any spacers, and thereafter the end portions of the fins may be “merged” by epitaxially growing a silicon material, which may result in complex manufacturing processes, thereby also possibly increasing the overall external resistance of the resulting drain and source regions.
For this reason, process strategies have been developed in which the semiconductor fins are formed in a “self-aligned” manner with respect to the gate electrode structure, wherein the semiconductor fins are restricted to the area covered by the gate electrode structure only, while the drain and source regions are preserved as continuous semiconductor regions, thereby eliminating any additional epitaxial growth techniques. Corresponding manufacturing strategies are, for instance, disclosed in non-published German patent applications by NDY et al. entitled “A self-aligned multiple gate transistor formed on a bulk substrate” and “A self-aligned fin transistor formed on a bulk substrate by late fin etch,” respectively. The disclosure of these German patent applications is herein incorporated by reference in its entirety.
Generally, these process strategies enable the formation of FinFET or multiple gate transistors on the basis of “two-dimensional” manufacturing processes so that three-dimensional transistors and conventional planar transistors may be provided concurrently without requiring separate processes except for the actual formation of the self-aligned semiconductor fins. Consequently, separate semiconductor devices in which the advantages of three-dimensional and two-dimensional transistors may be efficiently exploited may be fabricated on the basis of these process techniques, while at the same time not unduly contributing to the overall process complexity since many of the conventional two-dimensional process techniques, such as the formation of drain and source regions, gate electrode structures and the like, may be applied commonly for the multiple gate transistors and the planar transistors. Although the hybrid concept may basically have the potential of providing fast and powerful semiconductor devices at acceptable fabrication costs, it turns out that a significant variability of transistor characteristics, in particular of the threshold voltage of transistors of different gate length, is observed when comparing the multiple gate transistors with the planar transistors in the semiconductor device, as will be explained in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a perspective view of a semiconductor device 100 which may include multiple gate transistors, such as tri-gate transistors and planar transistors, according to the overall device requirements. For convenience, in FIG. 1a, a multiple gate transistor 150A is illustrated, while any planar transistors are not shown. The device 100 comprises a substrate 101, such as a silicon substrate, a silicon/germanium substrate or any other appropriate carrier material for forming thereon a semiconductor layer 102, for instance in the form of a silicon material. Generally, the semiconductor layer 102 is provided as a continuous semiconductor material at an initial manufacturing stage and may subsequently be divided into a plurality of semiconductor regions or active regions, wherein a single semiconductor region 102A is illustrated in FIG. 1a, in and above which the transistor 150A is formed. In other semiconductor regions, any other multiple gate transistors or planar transistors are provided in the device 100 as required in view of the overall circuit layout of the device 100. The semiconductor region 102A comprises a plurality of semiconductor fins 104 which are laterally positioned between a source region 151S and a drain region 151D. Furthermore, a dielectric material 103 is formed laterally adjacent to the semiconductor fins 104 and extends up to a height level that is recessed with respect to the surface of the semiconductor region 102A. In this manner, the dielectric material 103 substantially defines the electrically effective height of the semiconductor fins 104, which is to be understood as the vertical extension of the exposed portion of the semiconductor fins 104 in FIG. 1a. Moreover, a gate electrode structure 160A is provided above the semiconductor fins 104 and typically comprises an electrode material 162, such as a polysilicon material, an electrode metal and the like, in combination with a sidewall spacer structure 161 which may have any appropriate configuration. Furthermore, the gate electrode structure 160A comprises a gate dielectric material 163 which is provided so as to separate the electrode material 162 from the semiconductor fins 104, which represent the channel region of the transistor 150A. Consequently, the gate electrode material 163 is formed on a top surface 104T and on sidewall surface areas 104S of the semiconductor fins 104, while the electrode material 162 is formed on a dielectric material 163. Consequently, the sidewall surface areas 104S and the top surface 104T act as “planar” channel regions which are controlled by the “multiple” gate electrodes defined by the gate dielectric material 163 and the adjacent electrode material 162 formed on the corresponding surface areas 104T and 104S. Hence, in the configuration shown in FIG. 1a, the three surface areas 104S, 104T form a tri-gate configuration, wherein, however, the entire semiconductor fin 104 represents the channel region of the transistor 150A, which may thus be controlled by the combination of these multiple gates, as is also discussed above.
FIG. 1b schematically illustrates a perspective view of the device 100, wherein, for convenience, the gate electrode structure 160A (FIG. 1a) is not shown. Moreover, for convenience, a single semiconductor fin 104 is illustrated in FIG. 1b. As shown, the drain and source regions 151D, 151S have a dedicated lateral and vertical dopant profile which may be obtained on the basis of conventional planar transistor manufacturing techniques, for instance by performing implantation processes, so that the drain and source regions 151S, 151D electrically connect to the semiconductor fin 104, which acts as a channel region 152A of the transistor 150A, as discussed above.
FIG. 1c schematically illustrates a top view of the device 100 wherein the multiple gate transistor 150A is illustrated. For convenience, with the single semiconductor fin 104 acting as the channel region 152A for connecting the drain and source regions 151S, 151D, while, in a second semiconductor region 102B, a planar transistor 150B is provided in which a gate electrode structure 160B is formed above a planar channel region 152B that continuously laterally connects to drain and source regions 151S, 151D, respectively. The transistors 150A, 150B may have substantially the same gate length, i.e., in FIG. 1c, the horizontal distance between the drain and source regions 151S, 151D, and may also have substantially the same architecture with respect to the vertical and lateral dopant profile in the drain and source regions 151S, 151D since, as discussed above, the transistors 150A, 150B are typically formed by using process techniques that are commonly applied to the transistors 150A, 150B, except for the actual formation of the semiconductor fin 104.
For example, a typical process strategy for forming the semiconductor device 100 as shown in FIGS. 1a-1c may comprise the following process sequence. After forming the semiconductor regions 102A, 102B (FIG. 1c) by providing an appropriate isolation structure (not shown), which may include sophisticated lithography, etch, deposition, anneal and planarization techniques, the basic doping of the various semiconductor regions is established by using appropriate implantation and masking techniques. Thereafter, a mask may be formed so as to include a gate opening, which basically determines the lateral size and position of the gate electrode structures 160A, 160B. To this end, well-established deposition, lithography and etch techniques are applied. Thereafter, an appropriate hard mask is provided to define the position and lateral dimensions of the semiconductor fins 104 within the gate opening for the transistor 160A. To this end, any sophisticated deposition and patterning techniques are applied. Thereafter, an anisotropic etch process is performed to etch into the semiconductor region 102A, thereby forming the semiconductor fin 104 down to a specific depth. Thereafter, a dielectric material, such as silicon dioxide, is filled into the recesses laterally adjacent to the resulting semiconductor fin 104, while excess material is removed by planarization and etch techniques, thereby also adjusting a desired height level for the dielectric material 103 (FIG. 1b), thereby also adjusting the effective electrical height of the semiconductor fins 104. It should be appreciated that the semiconductor region 102B for the planar transistors is reliably covered by the hard mask in order to avoid any undue material erosion in a corresponding gate opening for the transistor 150B. After the removal of the hard mask, the gate electrode structures 160A, 160B may be formed by depositing any appropriate materials, such as a gate dielectric material 163 and the electrode material 162 (FIG. 1a), followed by the removal of the corresponding mask. In this manufacturing stage, the gate electrode structures 160A, 160B may be used as implantation masks for the further processing, i.e., for forming the drain and source regions 151S, 151D in order to establish the required complex vertical and lateral dopant profile. For example, the implantation sequences for forming the drain and source regions 151S, 151D may include an implantation process for incorporating drain and source dopant species with reduced implantation energy and possibly with reduced dose, while typically a counter-doping species is also incorporated, possibly on the basis of tilted implantation techniques, in order to adjust the overall transistor characteristics and in particular the threshold voltage of the transistors 150A, 150B. To this end, well-established masking regimes and implantation techniques, in combination with corresponding cleaning recipes that have to be provided upon removing a resist mask, are applied. Consequently, the various mechanisms that can influence the finally obtained threshold voltage of the transistors 150A, 150B are typically commonly applied to these transistors so that a change in threshold voltage of one type of transistor necessarily significantly affects the other type of transistor. It turns out, however, that the threshold voltages of the multiple gate transistors 150A significantly differ from the threshold voltages of the planar transistors 150B when transistors of different gate lengths are considered.
FIG. 1d schematically illustrates a typical dependency of the threshold voltage for planar and multiple gate transistors of different gate length when operated in a saturated state. Curve A represents the corresponding threshold voltage values for multiple gate transistors of gate lengths ranging from 22-54 nm, while curve B depicts the situation for the planar transistors 150B. Generally, the threshold voltages of the multiple gate transistors are significantly lower compared to the planar transistor which is assumed to be mainly affected by corner effects in the semiconductor fin 104. It is believed that one mechanism that results in a reduced threshold voltage is an increased segregation and out-diffusion of a well dopant species at the corner of the semiconductor fins 104. Furthermore, the overlap of the electric fields generated by the gate electrode structures acting from the top surface and the sidewall surface areas of the semiconductor fin 104, as discussed above, may also contribute to a reduced overall threshold voltage. Consequently, both geometry-dependent effects may result in higher electrostatic potential, lower conduction band energy and an increased current density at the corners of the semiconductor fins 104.
FIG. 1e schematically illustrates a typical doping concentration, for instance, in a section at the center of the semiconductor fin 104 and thus of the channel region 152A. As is evident from FIG. 1e, in the corner areas 104C of the fin 104, a reduced well dopant concentration is present which, as discussed above, in combination with a locally increased electric field, may result in higher current density in the corner areas 104C.
FIG. 1f schematically illustrates a corresponding simulation of the current density within the channel region 152A, thereby clearly indicating an increased charge carrier density at the corner areas 104C, thereby resulting in the overall reduced threshold voltage compared to the corresponding threshold voltage of the planar transistors, as is also evident from FIG. 1d when comparing curves A and B.
In order to reduce the mismatch of the threshold voltages between multiple gate transistors and planar transistors, in some strategies, the implantation of a counter-doping species into the channel regions, also referred to as halo implantation, is applied separately for the multiple gate transistors and the planar transistors. In this strategy, two additional implantation masks, implantation processes and associated cleaning steps are required for N-channel transistors on the one hand and P-channel transistors on the other hand. That is, the implantation sequence for forming halo regions, possibly in combination with corresponding drain and source extension regions, has to be performed twice for N-channel transistors and P-channel transistors in order to control the resulting threshold voltage differently for multiple gate transistors and planar transistors, respectively. In addition to significantly increased overall manufacturing costs, it turns out that the electrical behavior of the multiple gate transistors is degraded for different gate lengths, for instance in a range from 22-54 nm, in particular it turns out that only short channel transistors sufficiently respond to an increased counter-doping implantation dose in order to appropriately increase the threshold voltage (curve A in FIG. 1d), while, however, the multiple gate transistors of increased gate lengths, for instance of 54 nm, are hardly “degraded” due to less halo overlapping, while also the corner effects, described above with reference to FIGS. 1e and 1f, remain substantially unchanged. Furthermore, it has been observed that generally the dependency of the threshold voltage on the gate length of various transistors is more pronounced upon increasing the implantation dose of the counter-doping species or halo species upon forming the drain and source regions.
As a consequence, forming the complex vertical and lateral dopant profile of the drain and source regions separately, multiple gate transistors and planar transistors, for instance by separately using halo, i.e., counter-doping, implantation processes may result in a very complex manufacturing flow, while at the same time a significant mismatch between the multiple gate transistors and the planar transistors is still present, in particular for transistors having an increased gate length.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.